Prebuilt [SFFn] ASRock's DeskMini A300 - Finally!

TomHC81

Caliper Novice
May 21, 2020
27
11
www.sitepoint.sk
Sorry, but you did not quite answer what I asked for :)
I mean you started to talk about 5000 Series before. Do you have any evidence or are you just speculating? It is important to clarify what's known and what are own's statements if we are going to approach this topic seriously ;)
Hi Gustav, maybe I miss that info, but is there an official plan to release Renoir APUs into non-OEM market? Or the Renoir will be completely skipped for aftermarket and only Cezanne will be available for purchase?
Another theory how to enable S3 - it must be a single if/then/else statement disallowing S3 (and potentially other stuff) on PRO SKUs. Maybe we could "just" soemhow add PRO SKUs to a group of "regular" Renoirs? What could be the difference? Some feature bit, stepping, revision?
 

Valantar

SFF Guru
Jan 20, 2018
1,532
1,393
Hi Gustav, maybe I miss that info, but is there an official plan to release Renoir APUs into non-OEM market? Or the Renoir will be completely skipped for aftermarket and only Cezanne will be available for purchase?
Another theory how to enable S3 - it must be a single if/then/else statement disallowing S3 (and potentially other stuff) on PRO SKUs. Maybe we could "just" soemhow add PRO SKUs to a group of "regular" Renoirs? What could be the difference? Some feature bit, stepping, revision?
There's no indication that Renoir will ever see a desktop retail launch. It's too late for that to make any kind of sense economically.
 
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gustav

Cable-Tie Ninja
Jun 18, 2020
163
73
@TomHC81 I guess I can not answer your questions. No one can except AMD and/or partners.
I would also not expect Cezanne running on A300, it's just so high up in the sky. I would rather not believe or have no expectations at all. Therefore, if expectations are low, you can not get upset :) this is basically my strategy :D

Regarding S3 and PRO/non-PRO. S3 is a low level feature, which is either available or not. It is there (I would say like 95%, it's supported by the CPU, like all the CPUs after around the year 2000) but it's not implemented in our AGESA stack. AMD broke it once, and updated it's AGESA Firmware to fix it. But the problem is, the AsRock's support which is basically killing all of the experience for us. If Asrock does not update the stack, it's easier to exclude / hide the broken feature and to act like "well, it does not work" - it's simply cheaper.

I will believe S3 is there till you prove me wrong. (Please provide sources, not guessing "this" and "that")
Do not do trash-talk with no background checks before shouting it out into the community.
There are all kinds of people. People who are naively believing it's not there just because of "PRO" or some other guessing like this. It's no good for anyone :)

Ehm, you may ask ofcourse - How is it that this guy has such a strong opinion on the subject he's talking about?
I can answer - read for yourself :) it's all there...
You see, we're speaking about the ACPI standard, which is pre 2000-dated.
It describes system running modes. In regular case, most of the time, we are speaking about:
S0,S1..S3,S4,S5 https://en.wikipedia.org/wiki/Advanced_Configuration_and_Power_Interface#Global_states
They are well-defined and are present in modern x86 systems. Some of them, you may already stumbled on.

S0 : Regular running state of a system. CPU is not halted. The operating system is doing fine and you work actively. -- Here are technologies present known from earlier days e.g. Intel SpeedStep (Enchanced) or AMD Cool'n'Quite, which change the C-State of the CPU accordingly to be energy-efficient with the possibility to grab additional power when needed.
S1 : The CPU is halted, means "no clock", system state is being kept in RAM. CPU has still power, so cache-content is being kept
S2 : additionally to S1 the CPU looses it's power hence CPU-Registers and Cache (L1,L2,L3) are lost
S3 : This is what we know as "Stand-by" :) only RAM is kept alive, (almost same as S2 according to Microsoft)
S4 : Power off, but with the ability to restore the pervious session / context (hibernation)
S5 : is known as a Shutdown / Power-Off state (with wake on Power-Button, WOL, BIOS-Timer-Wakeup, etc)

Here even better reference:

Now use following command to check your firmware's (BIOS!) supported S-States:
> powercfg /a




My output saying:
----------------------------------------------------------
Following standby functions on this system available:
- Standby (S3)
- Hibernation
- Hybride Standby
- Fast Boot

Following standby functions on this system __not__ avaiable:
- S1 Standby: Not supported by the firmware of the system.
- S2 Standby: Not supported by the firmware of the system.
- S0 Standby (Low power Standby): Not supported by the firmware of the system.

Could I convince you? :)
For example by going from S0 to S3 on Renoir (or any other CPU) the system firmware (the BIOS therefore)
has to do the main task.
1. User triggers "Standby" on the start menu (just as an example)
2. The OS does it's thing to put processes asleep
3. OS triggers BIOS/UEFI function to copy CPU Caches and Registers into the RAM (since they get destroyed, it has to be taken care of)
4. BIOS runs its code to do all the copy job, flush CPU, putting it asleep and telling the Novuton Super I/O to flash the Power LED
5. system in S3
6. user wake up occurs (e.g. mouse movement)
7. UEFI / BIOS code is the first one to run recovering the system state, restoring the registers, etc
8. when done, BIOS passes over the control to the OS
9. you see your log-in screen

It's very much simplified. But do you see how many of this "basic functionality" the AGESA stack/BIOS firmware provides?
Now imagine, they do not update it... Could there be any possibility the S3 could be broken? :)
Far better: Somewhere I have read - it's a couple of days old - AMD admitted S3 problems on newer Chips, releasing new AGESA version later on ;)

Oh yea, and the Wake-On-LAN (WOL) feature is not working till this day. Well, it's S5 related, but still. You can see, there are bugs all over the place ;)

I may make mistakes as I'm partly recalling all those properties from my mind, feel free to correct me :)

From the found and posted earlier AGESA Plaform specs:

Page 38: Starting procedure, you CPU starts from it's reset-vector (A) then follow the path... (most of the times at (C) into "Main" below)
Basically the steps I mentioned from 4. to 7. but in a more detailed view, by AMD


Legend:

A — System reset. This occurs at first power-on of the system and also when system resets are performed by the software (warm reset).
B — Immediately after a reset some tasks must be performed in order to make a decision about the integrity of the ROM imag
C — The decision is made about the integrity of the ROM image. If the test fails, execution proceeds to the Recovery Mode. If the test passes, execution jumps to start the main boot sequence.
D — Recovery Mode. The software does minimal hardware initialization, locates the source for a new ROM image and initiates a Flash ROM updat
E — Main boot path. Proceed with full hardware initialization. Warm reset may be needed to instantiate new values into some register
F — Determine if the system is resuming from a suspend (ACPI S3) state. If yes, then jump to the restoration sequence.
G — Proceed to OS boot. Initialize all devices, create OS information tables, load the OS from storage, then jump to the OS entry.
H — Restoration. The system and OS state still reside in memory. Restart the system hardware devices, then re-enter the OS.

By now you should not have any doubts left. As you can see, S3 is part of the AGESA stack, which also the ACPI is a part of, and many many more.

I hoped to help out demystifying the S3 mode :D

Feel free to put a like, if I was able to provide any insights
Sincerely

Ah, last Edit, guessing: Therefore, you know the PRO processors have features like vPro on Intel's platform, where you can remotely go into BIOS of the system and able to maintain it from a remote source (basically optimal setting for a company's admin, see: https://www.amd.com/system/files/documents/ryzen-pro-article-ease-headaches-for-it-pros.pdf whitepaper) -- it will require the BIOS to handle the Sleep Modes in a different way. Therefore this "different way" is provided by AGESA and has to be implemented by the mobo's manufacturers. Here's another hint, why S3 does not work ;) ... and WOL in S5 should also work, which it does not even on non-PRO :) that's all of the magic

Additonal quote:
It speaks about AGESAv2 1.0.8.1 which should fix S3-wakeup-bug and RAID-Problems on the B550 based-boards.
So it's not some classified stuff you can not read up on the internet though ;) ... here you go

In german, summarized, AGESA firmware changelog, unofficial, highly recommended

PS.: Everytime I make - this is my feeling - such a longer, informative post, I also manage somehow to kill the thread for a while XD it's not an offence!
only when we speak about something, we can work all together to the solution to clarify things :D
 
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gustav

Cable-Tie Ninja
Jun 18, 2020
163
73
@A300 sorry, no XP regarding RAID-0/1 on A300... Usually you create in BIOS-like env your array and it's visible for windows as one volume, RAID0 - twice the size of your SDD (if both have same capacity) There is the RaidXpert Module in the FW, so I think it should be fine.

Back to the AGESA and O/C topic, based on coreboot--the opensource alternative for BIOS/UEFI:

Check both out, especially, the second one is referencing NDA docs from AMD (which we -- the publicity won't get to read)
PSP is highly intergrated in the ACPI -- there runs also some part of the code for S3 and S5 states, but that's not my main point.

0x12: SMU off-chip firmware section 2

  • Power Management firmware, responsible for system power/clock management.

1. https://github.com/coreboot/coreboot/tree/master/src/drivers/amd/agesa -- here happens AMD-specific magic, as I can see.
2. https://github.com/coreboot/coreboot/tree/master/src/soc/amd -- here should be looked at
3. https://github.com/coreboot/coreboot/tree/master/src/northbridge/amd -- this should be also interesting

https://doxygen.coreboot.org/dir_1ed2cc6c9ae198b199cb7e80f1efaf5d.html -- here docs the AGESA-chipset-based code

it's like a golden case, you have even in 2. 'romstages.c' -- there is everything the AGESA doc file ist speaking about:
Like especially: https://github.com/coreboot/coreboot/blob/master/src/soc/amd/picasso/romstage.c -- check the code:
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
FSP_M_CONFIG *mcfg = &mupd->FspmConfig;
const struct soc_amd_picasso_config *config = config_of_soc();

mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_mrc_cache();

mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS;
mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE;
mcfg->bert_size = CONFIG_ACPI_BERT_SIZE;
mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM);
mcfg->serial_port_stride = CONFIG(DRIVERS_UART_8250MEM_32) ? 4 : 1;
mcfg->serial_port_baudrate = get_uart_baudrate();
mcfg->serial_port_refclk = uart_platform_refclk();

mcfg->system_config = config->system_config;

if ((config->slow_ppt_limit_mW) &&
(config->fast_ppt_limit_mW) &&
(config->slow_ppt_time_constant_s) &&
(config->stapm_time_constant_s)) {
mcfg->slow_ppt_limit_mW = config->slow_ppt_limit_mW;
mcfg->fast_ppt_limit_mW = config->fast_ppt_limit_mW;
mcfg->slow_ppt_time_constant_s = config->slow_ppt_time_constant_s;
mcfg->stapm_time_constant_s = config->stapm_time_constant_s;
}

mcfg->ccx_down_core_mode = config->downcore_mode;
mcfg->ccx_disable_smt = config->smt_disable;

mcfg->sustained_power_limit_mW = config->sustained_power_limit_mW;
mcfg->prochot_l_deassertion_ramp_time_ms = config->prochot_l_deassertion_ramp_time_ms;
mcfg->thermctl_limit_degreeC = config->thermctl_limit_degreeC;
mcfg->psi0_current_limit_mA = config->psi0_current_limit_mA;
mcfg->psi0_soc_current_limit_mA = config->psi0_soc_current_limit_mA;
mcfg->vddcr_soc_voltage_margin_mV = config->vddcr_soc_voltage_margin_mV;
mcfg->vddcr_vdd_voltage_margin_mV = config->vddcr_vdd_voltage_margin_mV;
mcfg->vrm_maximum_current_limit_mA = config->vrm_maximum_current_limit_mA;
mcfg->vrm_soc_maximum_current_limit_mA = config->vrm_soc_maximum_current_limit_mA;
mcfg->vrm_current_limit_mA = config->vrm_current_limit_mA;
mcfg->vrm_soc_current_limit_mA = config->vrm_soc_current_limit_mA;
mcfg->sb_tsi_alert_comparator_mode_en = config->sb_tsi_alert_comparator_mode_en;
mcfg->core_dldo_bypass = config->core_dldo_bypass;
mcfg->min_soc_vid_offset = config->min_soc_vid_offset;
mcfg->aclk_dpm0_freq_400MHz = config->aclk_dpm0_freq_400MHz;
mcfg->telemetry_vddcr_vdd_slope_mA = config->telemetry_vddcr_vdd_slope_mA;
mcfg->telemetry_vddcr_vdd_offset = config->telemetry_vddcr_vdd_offset;
mcfg->telemetry_vddcr_soc_slope_mA = config->telemetry_vddcr_soc_slope_mA;
mcfg->telemetry_vddcr_soc_offset = config->telemetry_vddcr_soc_offset;
mcfg->hd_audio_enable = devtree_hda_dev_enabled();
mcfg->sata_enable = devtree_sata_dev_enabled();
}

I have no idea about 'FSPM_UPD - structure' this here is configuring the CPU, it or similar struct may configure the GFX.

Here is the code for the startup:
asmlinkage void car_stage_entry(void)
{
post_code(0x40);
console_init();

post_code(0x42);
u32 val = cpuid_eax(1);
printk(BIOS_DEBUG, "Family_Model: %08x\n", val); // this one you can see in the debug-coreboot git commit, below

/* Snapshot chipset state prior to any FSP call. */
fill_chipset_state();

post_code(0x43);
fsp_memory_init(acpi_is_wakeup_s3()); // you see how early it checks if it's a resume from S3 or not.
soc_update_mrc_cache();

memmap_stash_early_dram_usage();

post_code(0x44);
run_ramstage(); // this could be interesting for us, since here is RAM-stage, after the initial init and basic code in memory (?)

post_code(0x50); /* Should never see this post code. */
}

Additionally, extracted some debug-coreboot startup on Raven Ridge


https://doxygen.coreboot.org/da/dec/soc_2amd_2picasso_2include_2soc_2cpu_8h.html -- supported AMD CPUs by coreboot

Here the code, which triggers the line PSP boot mode: Development

It seems , at every cold boot, the PSP generated a timestamp, which is then used to valide things, maybe that is the difference @Danlopez1222 accountered?
It's very time-consuming to read through the code...

One sidenote -- very interesting, looking at GPIO/I2C definitions and configuration, i can see, where Channel 2 gets initialized, but kinda "the other half is missing" -- it should be inside the PSP firmware. One interesting thing, I came across is "#define SOC_GPIO_TOTAL_PINS 145" which tells me that out of all those
PINS only 145 are used to communicate with the outer world outside of SOC and it's Memory Architecture. Very interesting :)


Greetings
 
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alles_alles

SFF Lingo Aficionado
Aug 11, 2020
101
26
i am so insane, but i bought x300, now. there, the firmware is not better. no technical environments or inovation nuclear power free developlemt... jaja just a joke!
i do not know what the problem of asrock is.... i hate the case, + mount the 2 USB-cables it is annoying to close case to 100%, again. as like as at the a300. that is still expansive metal trash. but it is small, that i am liking.
what i want to say:
i took my settings into the x300. OS is arch-linux. OK, first good news is: now I can boot Linux Mint (USB-Live-Stick) without producing CMOS crash!
Arch works with adopting new NVRAM chroot method to efibootmgr adding .... i am not so good in english!

So i tested now my last moments before i changed to x300.
booting - start lutris - epic games - jurassic park.
that i was play lots of hours in the last days.
now, it is in ~1h hang the whole system. complete freeze. there is no reset-button, you know it. so push the power-button. ahhh that i did not awaiting-.-

and the other thing is booting: journalctl -xb
Jan 30 00:36:13 archlinux kernel: __common_interrupt: 1.55 No irq handler for vector
Jan 30 00:36:13 archlinux kernel: #2
Jan 30 00:36:13 archlinux kernel: __common_interrupt: 2.55 No irq handler for vector
Jan 30 00:36:13 archlinux kernel: #3
Jan 30 00:36:13 archlinux kernel: __common_interrupt: 3.55 No irq handler for vector
Jan 30 00:36:13 archlinux kernel: #4
Jan 30 00:36:13 archlinux kernel: __common_interrupt: 4.55 No irq handler for vector
Jan 30 00:36:13 archlinux kernel: #5
Jan 30 00:36:13 archlinux kernel: __common_interrupt: 5.55 No irq handler for vector
Jan 30 00:36:13 archlinux kernel: #6
Jan 30 00:36:13 archlinux kernel: __common_interrupt: 6.55 No irq handler for vector
Jan 30 00:36:13 archlinux kernel: #7
Jan 30 00:36:13 archlinux kernel: __common_interrupt: 7.55 No irq handler for vector
...
an 30 00:36:13 archlinux kernel: system 00:04: [io 0x0910-0x091f] has been reserved
Jan 30 00:36:13 archlinux kernel: system 00:04: [mem 0xfec00000-0xfec00fff] could not be reserved...

and i will found more.
i just changed the motherboard.

asrock need a complete new and better uefi-firmware development team.

some infos about me: i did years nothing in computer. just youtubing and google-ing 8years with old notebook.
my primary OS was linux mint.
i am using arch, because A300+P1+LM= kill CMOS, and because bad supporters i have the same settings still today.
with Arch my settings was running, but Arch is more difficult as Mint. And primary i just wanted googleing and facebooking and send dirty letters in thunderbird for my imaginary friends.... -.-

now i am a priceless product tester and annoy all users, because "debug".

later a300 -> mama #birthday-present. she using windows. ok she needs some new hardware, but she has just 100mb/sec hdd computer and other dinosaur hardware. with Firmware 3.60k she would´t have trouble with this product.

back to x300:
what uefi-firmware you will offer me? actual installed P1.40.

----
update:
i upgrade the firmware to P1.46 (X300)
i have some bugs in my bootscreen, will see later.
Jurassic Park works fine as like as A300 with Firmware 3.60k
do you upgrade it on deskmina a300 with p1-46 (x300) bios ?
 

ssouthall6

Chassis Packer
Jun 18, 2020
18
8
Pretty happy with the fairly straightforward upgrade from 3200g to 4650g, other than forgetting to suspend bitlocker on one of my SSD's and faffing around with those nasty little cables on the base it seems to finally be aligned with the 64gb ram
 
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A300

Average Stuffer
Jul 13, 2019
67
14
Hi guys,

What's the maximum supported refresh rate at 1980x1280 on A300?

Manual did not state clearly about this.
 
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limsandy

Trash Compacter
Jul 3, 2020
45
22
Pretty happy with the fairly straightforward upgrade from 3200g to 4650g, other than forgetting to suspend bitlocker on one of my SSD's and faffing around with those nasty little cables on the base it seems to finally be aligned with the 64gb ram

Cool.... May I ask how high were you able to overclock your DDR4 memory and which version BIOS you have now? Thanks in advance! :D
 
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ssouthall6

Chassis Packer
Jun 18, 2020
18
8
Cool.... May I ask how high were you able to overclock your DDR4 memory and which version BIOS you have now? Thanks in advance! :D
Hi, 3.60S and I didn't bother overclocking the RAM, it's dual channel 3200 and it's running fast enough for me. Just need a nicer case now to include the brick!
 

A300

Average Stuffer
Jul 13, 2019
67
14
Hi, 3.60S and I didn't bother overclocking the RAM, it's dual channel 3200 and it's running fast enough for me. Just need a nicer case now to include the brick!
There is an itx case that already included 200 watt power brick.

Perhaps, with some modifications, A300 board could fit in it.

Look at Inwin B1 case.
 
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Nunuji

Chassis Packer
Jan 17, 2021
19
7
Cool.... May I ask how high were you able to overclock your DDR4 memory and which version BIOS you have now? Thanks in advance! :D
I managed to get a 3600 CL16 overclock on my 3200 CL16 RAM with the 4650g. I'm on BIOS 3.60R.
The overclock depends on a LOT of things though, so your results may vary.

Oh, @gustav , I had a little bit of time to test my system using a different A300, and it seems to be working on that other motherboard, so I think I did do some minor damage to mine. I would love to find what was damaged on my A300 board, but there is no visual damage and I don't really have the tools or know-how, so I am just going to assume it is the VRM.
 
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A300

Average Stuffer
Jul 13, 2019
67
14
Off topic :

After watched 5980HS performance on ROG Flow 13 on YouTube video, I think, AMD hold back performance on their desktop CPU for marketing purpose.

This 5980HS can stable reached about 2100 score in CB15 every time it runs with temp around 80-85C in that tiny ultrabook case.

This score is comparable with 4750G/3700X, but this is the 65W TDP CPU, while 5980HS is only 45W TDP.
 

Nunuji

Chassis Packer
Jan 17, 2021
19
7
Off topic :

After watched 5980HS performance on ROG Flow 13 on YouTube video, I think, AMD hold back performance on their desktop CPU for marketing purpose.

This 5980HS can stable reached about 2100 score in CB15 every time it runs with temp around 80-85C in that tiny ultrabook case.

This score is comparable with 4750G/3700X, but this is the 65W TDP CPU, while 5980HS is only 45W TDP.
If I remember correctly (someone please correct me if I am mistaken. ^^; ), the desktop 4000 series and laptop 5000 series are completely different generations and so I probably wouldn't recommend drawing conclusions like that from comparing them. As far as I know, the 4000 series desktop APUs were rebranded 3000 series desktop CPUs (Zen2), just like the 3000 series APUs were rebranded 2000 series (Zen+) chips and so on, whereas the 5980HS is ACTUALLY a 5000 series chip (Zen3).

Plus their L3 caches are different and I'm pretty sure cinebench really likes cores/threads and large caches. Oh, and TDP is kinda a made-up equation anyway where they could change specific variables to create whatever TDP target they want. (Source: Gamers Nexus)
 
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Valantar

SFF Guru
Jan 20, 2018
1,532
1,393
It's even more complicated. AMD is mixing Zen2 and Zen3 in Ryzen 5000u laptop series.
5800u = zen3
5700u = zen2
5600u = zen3
5500u = zen2
5400u = zen3
5300u = zen2
Yeah, that's a bit of a bummer. My guess is it's a cost savings, as the large Cezanne die is inevitably more expensive to produce than the smaller Lucienne die, saving them the cost of cutting down Cezanne too far for low-end chips. Btw, there is no 5400U. Lowest end Zen3 is 5600U. And frankly, this is perfectly fine given how good Zen2 still is. And it isn't just a rebrand of Renoir, as it has additional power saving features that are bound to be quite valuable in thin-and-light laptops.

Still confusing though.

Off topic :

After watched 5980HS performance on ROG Flow 13 on YouTube video, I think, AMD hold back performance on their desktop CPU for marketing purpose.

This 5980HS can stable reached about 2100 score in CB15 every time it runs with temp around 80-85C in that tiny ultrabook case.

This score is comparable with 4750G/3700X, but this is the 65W TDP CPU, while 5980HS is only 45W TDP.
As @Nunuji said above, this is due to 5000-series (high end) APUs being Zen3, not Zen2. That's a ~19% IPC bump, plus clock speed increases due to a more mature process node. Mobile chips are also binned better than desktop chips (whether for efficiency only (U-series) or efficiency at high clocks (H-series)). That means you'll always be able to get more performance out of a mobile part than a desktop part at the same wattage, and they might even exceed higher-rated desktop parts in edge cases.

So AMD aren't holding back anything, they just brought their mobile APUs up to speed with their best desktop parts.