Now we're talking
This is with 85W TDP, unlimited CPU frequency and an iGPU Curve Optimizer of -10 (GFX CO -15 is already unstable for me).
Since GFX CO -10 increases iGPU frequency (up to max frequency, 2900MHz in the 8700G) due to it having more power headroom (from undervolting), it starts triggering more often the current limit. For this reason, I maxed both CPU's TDC and EDC so it can stretch its legs at lower voltages (strangely iGPU current limit is in some way limited by those values instead of SOC current limits as Ryzen Master suggests). This shouldn't be a problem, specially since I am not pushing the TDP above CPU's default values.
Undervolting the iGPU has no effect if it always have available power budget (if TDP is high enough). I personally change the TDP based on what I'm playing, since there is usually a point where more power doesn't translate to more performance (those are the shortcuts I have at the bottom bar).
If you plan to undervolt the iGPU, do it after adjusting the memory frequency/timings, since higher iGPU loads affect how much you can undervolt it.
At lower TDPs, you can get more iGPU performance by limiting the CPU frequency (to free power budget for the iGPU), since most of the time you will be iGPU limited. Generally, the lower the FPS the more you can limit the CPU frequency. In 3D Mark Time Spy since the FPS is so low with my 8700G I get the best GPU score by limiting the CPU frequency to its lowest value (2.35GHz) via windows power plan.
I am quite impressed since I am now getting the same GPU Score with 45W as I was getting with 6200 MT/s at 65W.
I am using Dual Rank memory, which behaves differently from Single Rank, therefore your experience will probably different than mine. What I can say is that MEM VDD, MEM VDDQ, CPU VDDIO, CPU VSOC and cLDO VDDP (this last one specially for Dual Rank) plays a big role and it is not obvious how. There must be some intricate relationships between those voltages that affect stability (we already got a hint of this from the available documentation stating that VSOC needs to be lower than VDDIO + 100mv despite coming from different voltage rails).
In my experience, on high frequencies lowering both VDDQ (to 1.2v) and VSOC (as low as it could go) helped with stability, which is something I wasn't expecting. But as I was adjusting VDDQ, adjusting VDDIO also seemed to be necessary, and by extension VDDP since it derives from it. In the end I just tried as many combinations as possible, running simple stress tests (like p95) as guidance to find the most stable combinations (I recommend you to use a spreadsheet for this).
Regarding the timings:
My memory have Hynix A-Die (as most DDR5 memory actually, except 24/48GB dimms which have Hynix M-die, which is almost identical to A-die)
- Some people recommend you to start with the primaries (tCL, tRCD and tRP) but I didn't do that because those are the most affected by MEM VDD (memory voltage) and I'm still deciding which memory voltage I want to run daily.
- tRAS I just set to the conventional tRCD (row activation time) + tRTP (read to precharge)
- tRC should always be tRAS + tRP
- tRRD(L/S) and tFAW limits the amount of row activations in a given timeframe (this is supposed to help with internal voltage drops). I have them set at the minimum possible value, although tRRDS is not supposed to give any benefits below 8, so I should probably leave it at that (and adjust tFAW accordingly to 4x tRRDS = 32).
- tRTP is not supposed to go lower than 12 so I have it maxed, although you can set it lower to the point of instability for some reason
- tWR (delay after write) can't go lower than 48 and from that up in multiples of 6.
- tWTR(L/S) (write to read delay) are maxed out too at 16/4 respectively.
- tRDWR and tWRRD which are related to delays between read-to-write and vice versa are also maxed at 16/1
- Then you have tRDRDscl and tWRWRscl timings which are extremely important for bandwidth. This you want to have them as low as possible and vary a lot based on memory frequency. tRDRDscl (read-to-read) at 4 is probably as low as it can go. tWRWRscl value depends on tRDRDscl and is probably ignored by the memory controller since no one is setting it correctly (you can test this by setting it to 1 and it works). The actual value is tWRWRscl = (tRDRDscl + 7) x 2 - 7 since those timings actually come from another timing that is hidden (CCDL) and that's the one you're actually setting (tRDRDscl = CCDL - 7; tWRWRscl = CCDLWR - 7; CCDLWR = CCDL * 2)
- tRDRDSC and tWRWRSC should always be 1, otherwise you'll start adding unnecessary gaps between read/write bursts
- tRDRD(SD/DD) and tWRWR(SD/DD) are only relevant in multiple rank (SD = same channel, different rank) and multiple dimms per channel (i.e. 4 dimms) (DD = same channel, different dimm) configurations. If that's what you have, start with a high values and lower it slowly testing thoroughly for stability.
- And finally the refresh timings: tREFI (how often a refresh happens) and tRFC (refresh duration). tRFC2 and tRFCsb are not used.
- It seems that this BIOS version doesn't allow you to set tRFC to something different than tRFC2, so set both at the same value.
- I was able to run close to 130ns refresh duration at low speeds, but it seems that at high speeds I need above 145ns (probably due to heat, since refresh is very sensitive to memory temps). For this reason I recommend you to adjust this timing last once the memory is fully stressed.
By the way, FFXIV Dawntrail Benchmark seems to be extremely good at detecting unstable memory/infinity fabric (better than Time Spy), probably due to it being very hard on memory in many different ways. Run it with the "Maximum" profile, since other profiles have dynamic FSR based on FPS and you want something that behaves the same all the time.
Now I have to start running all the usual memory test programs (y-cruncher, p95, TM5, etc) to make sure this is stable.