Very interesting to see, the SFF gods are thankful for your sacrifice.
Just a question, but what do you mean in the last picture with
"It would be interesting to know whether the contact pairs that leave the connector are the ones that are designed as differential pairs in the PCIe spec"
So in the picture you can see that most contacts have the pattern of two being connected to traces on the board that lead to two pins which are close together and the next two being connected to the ground plane.
PCIe uses differential signaling to reduce the influence of EMI on the signal quality, so for every transmitter or receiver (which together form one lane), the connector has two pins, each of which carries the negative voltage of its counterpart.
What I deduct from that is that the two traces that lead to two adjacent wires in the ribbon cable are correspondent to the pins that form those differential signal pairs.
I just looked at the PCIe spec and the pinout seems to correspond pretty much exactly with the ribbon cable and the traces on the PCB, so maybe I should remove that comment from the picture.
So from what I can tell, its cross section is:
Tape -> cable -> copper foil -> cable -> Tape
And the copper foil is there to prevent crosstalk between the 2 ribbon cables.
Now my question is, given those outer tapes are electrically conductive (that's the only way for them to prevent external EMI), but in that last photo, it looks like the tape goes (lengthwise) all the way to the leads on the PCB on both ends. Wouldn't that short something? Or somehow, they managed for the tape to touch only the ground leads, and nothing else?
As you can see in picture 6 ("The braiding"), the conductive layer on the tape isn't covering the whole tape. It is a separate layer that is glued on to the outer, non-conductive braiding during assembly. Where it could come into contact with the solder connections, it is not present on the braiding.
That's interesting, the Tx and Rx lanes are shielded from each other, and both are shielded from external EMF, but there appears to be effectively no crosstalk protection between adjacent pairs (pairs are not themselves shielded, no alternating-prime twist ratios).
However, if the root of the issue is near-end crosstalk between the 'high' power Tx lane and it's adjacent Rx lane (i.e a device puts energy into the Tx line, this energises the adjacent Rx line, and the device 'receives' it's own outgoing signals at a higher level than the incoming 'real' signals) that may be sufficient for the relatively short ranges these extenders operate at (i.e. extenders not long enough for pair-to-pair crosstalk to be an issue).
Well, as you can see in the last picture, there are always at least two grounded wires between each differential pair, which corresponds to the pinout of the connector specified by the PCIe spec, so that should prevent most crosstalk between those pairs. It is true that there is no twisting going on in this ribbon, though.
From what we know, this riser performs a little less well than the 3M one, so that might be the reason why.
The shielding between Rx and Tx is the most basic thing I expect from such a riser, the PCIe connector is designed in such a way that you have Rx on one and Tx on the other side, so if you're using a triple-layer board, having a ground plane in the middle already prevents such crosstalk. The same can be said for rigid PCIe risers, and those aren't shielded against pair-crosstalk either, are they?
