That doesn't really apply to what I was saying. PLX chips take a given "bundle" of PCIe lanes from whatever source and uses them as an uplink for its own switched lanes, all of which will have the same latency (at least per connected device). My guess from looking at the hardware SLI switch pictured above was that it only switched the latter 8 lanes of the first slot (as those are the only ones that need switching for SLI, and this would drastically simplify routing to the switch), leaving the first 8 directly connected to the first slot. If this was the case, the latter 8 lanes would have significantly longer traces (down past the PCIe slot, down to the switch socket, onto the switch, back off again, up to the PCIe slot) than the former 8 (down to the socket, done) when used as a monolithic x16 block. Of course, the switch might switch all 16 (it certainly looks to have enough pins), but I assumed that would complicate routing too much to be feasible in that position. I might of course be wrong. I don't expect this was a cheap board.