Normal
Tricky, yes, but there is considerable risk management before assembly (EDS of all chips before stacking, etc). In any case, with HBM1 there were redundant TSVs that allow a degree of defect while still functioning normally, just like how DRAM and flash are made with slightly more capacity than will be advertised. It's reasonable to assume that HBM2 also has such test TSVs.Not all stacks survive, and this is true of any manufacturing process, but how much yield loss is the result is questionable.
Tricky, yes, but there is considerable risk management before assembly (EDS of all chips before stacking, etc). In any case, with HBM1 there were redundant TSVs that allow a degree of defect while still functioning normally, just like how DRAM and flash are made with slightly more capacity than will be advertised. It's reasonable to assume that HBM2 also has such test TSVs.
Not all stacks survive, and this is true of any manufacturing process, but how much yield loss is the result is questionable.
